RISC-V: Enabling the compute architectures for a new generation of vehicles

By Pete Lewin of RISC-V
Time: 16:00 Room: S5

Abstract

An intense period of innovation is driving the automotive supply chain to reimagine compute architectures, requiring companies to take more control of their computing platforms, specifying new architectures based on the demands, constraints and opportunities of automotive applications.
RISC-V is an open standard Instruction Set Architecture (ISA) that enables companies the freedom to design their best possible processors for their application. Over 10 billion RISC-V cores have already shipped, with this adoption spreading innovation across all domains and performance points.
The RISC-V ecosystem of member companies delivers the technologies and tools to develop these new platforms with flexible multi-sourcing across a range of development options from buying chips, to licensing processor IP, to designing your own cores. Joining as a member of RISC-V enables you to be part of the conversations shaping the future of the standard.
RISC-V enables design flexibility and freedom, delivering levels of customisation not possible with other compute architectures.Come to this talk by Peter Lewin, the Chair of the Automotive Special Interest Group, to find out more about RISC-V and its ecosystem and how it can enable the next generation of automotive computing.

Biography

Pete looks after the RISC-V CPU ecosystem at Imagination technologies. Prior to this he worked for over 20 years in the CPU IP business in various technical, marketing and business roles supporting complex ecosystems encompassing tools, software and hardware from companies across the industry. Pete is passionate about bringing diverse companies together to create joint outcomes that are better than the sum of the parts. He is also Chair of the RISC-V Automotive Special Interest Group.